1. Field of the Invention
This disclosure relates to semiconductor devices, and more particularly to a semiconductor device that includes a capacitor having an improved structural stability and an enhanced capacitance, and a method of manufacturing the semiconductor device.
2. Description of the Related Art
In general, semiconductor memory devices such as dynamic random access memory (DRAM) devices can store data or information therein. The data or information may be stored to as well as read out from the semiconductor memory devices. A typical single unit memory cell of the semiconductor memory device includes one capacitor and one transistor. The capacitor typically includes a storage electrode, a dielectric layer, and a plate electrode. To improve a storage capacitance of the semiconductor memory device, a capacitor having a high capacitance is required.
As the semiconductor memory device becomes highly integrated, the area of the unit memory cell is reduced. To ensure a sufficient storage capacitance of the semiconductor memory device, the capacitor may have various shapes such as a box, a cylinder, etc. However, as the design rules for semiconductor memory devices rapidly decrease, the aspect ratio of the capacitor increases because the capacitor must be formed in a correspondingly smaller unit area of the semiconductor memory device. The aspect ratio is defined as the ratio between a height of the capacitor and a width of the capacitor. As a result, adjacent capacitors having high aspect ratios may lean against each other, causing them to become electrically connected and generating a two-bit short between the adjacent capacitors.
To overcome the above problem, a semiconductor memory device and a method of manufacturing the same, which are capable of improving a mechanical strength of a capacitor by connecting lower electrodes to each other using an insulation member having a beam shape, are disclosed in U.S. Patent Application Publication No. 2003-85420.
FIG. 1A is a cross-sectional diagram illustrating a semiconductor device that was disclosed in U.S. Patent Application Publication No. 2003-85420. FIG. 1B is a plan diagram further illustrating the semiconductor device of FIG. 1A.
Referring to FIGS. 1A and 1B, an isolation layer 13 is formed on a substrate 10 to divide the substrate 10 into an active region and a field region. Gate structures 22 are formed in the active region of the semiconductor substrate 10. Each of the gate structures 22 includes a gate oxide layer pattern, a gate electrode, and a mask pattern.
Impurities are implanted into a surface of the semiconductor substrate 10 by an ion implantation process using the gate structures 22 as a mask to form source/drain regions 16 and 19 at the surface portions of the substrate 10 between the gate structures 22. Thus, metal oxide semiconductor (MOS) transistors are formed on the semiconductor substrate 10.
A first insulating interlayer 37 is formed on the substrate 10 and the MOS transistors. Capacitor plugs 25 and a bit line plug 28 are formed through the first insulating interlayer 37. The capacitor plugs 25 and the bit line plug 28 are connected to the source/drain regions 16 and 19, respectively.
A second insulating interlayer 40 is formed on the first insulating interlayer 37. The second insulating interlayer 40 is partially etched to form a bit line contact plug 31 making contact with the bit line plug 28. A third insulating interlayer 43 is formed on the second insulating interlayer 40. The third and second insulating interlayers 43 and 40 are successively etched to form capacitor contact plugs 34 making contact with the capacitor plugs 25, respectively.
An etching stop layer 46 is formed on the third insulating interlayer 43 and the capacitor contact plugs 34. Holes 49 that expose the capacitor contact plugs 34 are formed through the etching stop layer 46. Cylindrical bottom electrodes 52 that make contact with the capacitor contact plugs 34 are formed in the holes 49, respectively. Here, the cylindrical bottom electrodes 52 are electrically connected to the source/drain regions 16 through the capacitor contact plugs 34 and the capacitor plugs 25.
Beam-shaped insulating members 64 are formed between sidewalls of adjacent bottom electrodes 52. Dielectric layers 55 and top electrodes 58 are successively formed on the bottom electrodes 52 to thereby form capacitors 61 on the semiconductor substrate 10.
An additional insulation layer is formed over the substrate 100 to cover the capacitors 61 Since the beam-shaped insulating members 64 are formed between the sidewalls of the adjacent bottom electrodes 52, the mechanical strength of the capacitor may be improved.
However, in the above-described semiconductor device, the processes for manufacturing the semiconductor device may be complicated because a plurality of beam-shaped insulating members 64 should be formed between the adjacent bottom electrodes 52, although the mechanical strength of the capacitor 61 may be improved through the beam-shaped insulating member 64. Thus, cost and time for manufacturing the semiconductor device may be increased. Additionally, the manufacturing processes may be more complicated because the capacitor 61 has a complex structure including the bottom electrode 52, the beam-shaped insulating members 64, the dielectric layer 55, and the top electrode 58. Furthermore, the additional insulation layer may not be precisely formed between the capacitors 61 having the complex structure so that the capacitors 61 may be electrically connected to an upper wiring 67 formed on the capacitors 61. As a result, the processes for manufacturing the semiconductor device including the capacitor 61 having the complex structure may have poor throughput.
Embodiments of the invention address these and other disadvantages of the conventional art.